169 lines
5.1 KiB
Plaintext
169 lines
5.1 KiB
Plaintext
This chapter documents the Backend for the 80x86 microprocessor family.
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@section Legal
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This module is written in 2005-2006,2011,2015-2016 by Frank Wille and
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is covered by the vasm copyright without modifications.
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@section Additional options for this module
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This module provides the following additional options:
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@table @option
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@item -cpudebug=<n>
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Enables debugging output.
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@item -m8086
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Generate code for the 8086 CPU.
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@item -mi186
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Generate code for the 80186 CPU.
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@item -mi286
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Generate code for the 80286 CPU.
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@item -mi386
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Generate code for the 80386 CPU.
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@item -mi486
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Generate code for the 80486 CPU.
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@item -mi586
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Generate code for the Pentium.
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@item -mi686
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Generate code for the PentiumPro.
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@item -mpentium
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Generate code for the Pentium.
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@item -mpentiumpro
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Generate code for the PentiumPro.
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@item -mk6
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Generate code for the AMD K6.
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@item -mathlon
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Generate code for the AMD Athlon.
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@item -msledgehammer
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Generate code for the Sledgehammer CPU.
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@item -m64
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Generate code for 64-bit architectures (x86_64).
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@end table
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@section General
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This backend accepts 80x86 instructions as described in the
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Intel Architecture Software Developer's Manual.
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The target address type is 32 bits. It is 64 bits when the x86_64
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architecture was selected (@option{-m64}).
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Instructions do not need any alignment. Data is aligned to its natural
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alignment by default.
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The backend uses MIT-syntax! This means the left operands are always the
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source and the right operand is the destination. Register names have to
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be prefixed by a '%'.
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The operation size is indicated by a 'b', 'w', 'l', etc. suffix directly
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appended to the mnemonic. The assembler can also determine the operation
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size from the size of the registers being used.
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@section Extensions
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Predefined register symbols in this backend:
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@itemize @minus
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@item 8-bit registers: @code{al cl dl bl ah ch dh bh axl cxl dxl spl bpl sil dil r8b r9b r10b r11b r12b r13b r14b r15b}
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@item 16-bit registers: @code{ax cx dx bx sp bp si di r8w r9w r10w r11w r12w r13w r14w r15w}
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@item 32-bit registers: @code{eax ecx edx ebx esp ebp esi edi r8d r9d r10d r11d r12d r13d r14d r15d}
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@item 64-bit registers: @code{rax rcx rdx rbx rsp ebp rsi rdi r8 r9 r10 r11 r12 r13 r14 r15}
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@item segment registers: @code{es cs ss ds fs gs}
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@item control registers: @code{cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15}
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@item debug registers: @code{dr0 dr1 dr2 dr3 dr4 dr5 dr6 dr7 dr8 dr9 dr10 dr11 dr12 dr13 dr14 dr15}
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@item test registers: @code{tr0 tr1 tr2 tr3 tr4 tr5 tr6 tr7}
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@item MMX and SIMD registers: @code{mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11 xmm12 xmm13 xmm14 xmm15}
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@item FPU registers: @code{st st(0) st(1) st(2) st(3) st(4) st(5) st(6) st(7)}
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@end itemize
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This backend extends the selected syntax module by the following
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directives:
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@table @code
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@item .code16
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Sets the assembler to 16-bit addressing mode.
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@item .code32
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Sets the assembler to 32-bit addressing mode, which is the default.
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@item .code64
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Sets the assembler to 64-bit addressing mode.
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@end table
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@section Optimizations
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This backend performs the following optimizations:
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@itemize @minus
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@item Immediate operands are optimized to the smallest size which can
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still represent the absolute value.
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@item Displacement operands are optimized to the smallest size which
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can still represent the absolute value.
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@item Jump instructions are optimized to 8-bit displacements, when possible.
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@end itemize
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@section Known Problems
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Some known problems of this module at the moment:
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@itemize @minus
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@item 64-bit operations are incomplete and experimental.
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@end itemize
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@section Error Messages
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This module has the following error messages:
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@itemize @minus
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@item 2001: instruction not supported on selected architecture
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@item 2002: trailing garbage in operand
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@item 2003: same type of prefix used twice
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@item 2004: immediate operand illegal with absolute jump
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@item 2005: base register expected
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@item 2006: scale factor without index register
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@item 2007: missing ')' in baseindex addressing mode
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@item 2008: redundant %s prefix ignored
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@item 2009: unknown register specified
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@item 2010: using register %%%s instead of %%%s due to '%c' suffix
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@item 2011: %%%s not allowed with '%c' suffix
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@item 2012: illegal suffix '%c'
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@item 2013: instruction has no suffix and no register operands - size is unknown
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@item 2015: memory operand expected
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@item 2016: you cannot pop %%%s
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@item 2017: translating to %s %%%s,%%%s
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@item 2018: translating to %s %%%s
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@item 2019: absolute scale factor required
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@item 2020: illegal scale factor (valid: 1,2,4,8)
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@item 2021: data objects with %d bits size are not supported
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@item 2022: need at least %d bits for a relocatable symbol
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@item 2023: pc-relative jump destination out of range (%lld)
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@item 2024: instruction doesn't support these operand sizes
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@item 2025: cannot determine immediate operand size without a suffix
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@item 2026: displacement doesn't fit into %d bits
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@end itemize
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