125 lines
3.3 KiB
Plaintext
125 lines
3.3 KiB
Plaintext
This chapter documents the Backend for the c16x/st10 microcontroller family.
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Note that this module is not yet fully completed!
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@section Legal
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This module is written in 2002-2004 by Volker Barthelmann and
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is covered by the vasm copyright without modifications.
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@section Additional options for this module
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This module provides the following additional options:
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@table @option
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@item -no-translations
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Do not translate between jump instructions.
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If the offset of a @code{jmpr}
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instruction is too large, it will not be translated to
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@code{jmps} but an error will be emitted.
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Also, @code{jmpa} will not be optimized to @code{jmpr}.
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The pseudo-instruction @code{jmp} will still be translated.
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@item -jmpa
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A @code{jmp} or @code{jmpr} instruction that is translated due to
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its offset being larger than 8 bits will be translated to a
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@code{jmpa} rather than a @code{jmps}, if possible.
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@end table
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@section General
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This backend accepts c16x/st10 instructions as described in the
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Infineon instruction set manuals.
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The target address type is 32bit.
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Default alignment for sections and instructions is 2 bytes.
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@section Extensions
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This backend provides the following specific extensions:
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@itemize @minus
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@item
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There is a pseudo instruction @code{jmp} that will be translated
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either to a @code{jmpr} or @code{jmpa} instruction, depending on
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the offset.
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@item
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The @code{sfr} pseudo opcode can be used to declare special function
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registers. It has two, three of four arguments. The first argument
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is the identifier to be declared as special function register.
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The second argument is either the 16bit sfr address or its 8bit base
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address (0xfe for normal sfrs and
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0xf0 for extended special function registers). In the latter case,
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the third argument is
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the 8bit sfr number. If another argument is given, it specifies the
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bit-number in the sfr (i.e. the declaration declares a single bit).
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Example:
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@example
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.sfr zeros,0xfe,0x8e
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@end example
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@item
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@code{SEG} and @code{SOF} can be used to obtain the segment or
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segment offset of a full address.
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Example:
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@example
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mov r3,#SEG farfunc
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@end example
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@end itemize
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@section Optimizations
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This backend performs the following optimizations:
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@itemize @minus
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@item
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@code{jmp} is translated to @code{jmpr}, if possible. Also, if
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@option{-no-translations} was not specified, @code{jmpr} and
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@code{jmpa} are translated.
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@item
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Relative jump instructions with an offset that does not fit into
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8 bits are translated to a @code{jmps} instruction or an inverted
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jump around a @code{jmps} instruction.
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@item
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For instruction that have two forms @code{gpr,#IMM3/4} and
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@code{reg,#IMM16} the smaller form is used, if possible.
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@end itemize
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@section Known Problems
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Some known problems of this module at the moment:
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@itemize @minus
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@item Lots...
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@end itemize
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@section Error Messages
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This module has the following error messages:
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@itemize @minus
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@item 2001: illegal operand
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@item 2002: word register expected
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@item 2004: value does not find in %d bits
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@item 2005: data size not supported
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@item 2006: illegal use of SOF
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@item 2007: illegal use of SEG
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@item 2008: illegal use of DPP prefix
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@end itemize
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