249 lines
6.9 KiB
Plaintext
249 lines
6.9 KiB
Plaintext
This chapter documents the backend for the Advanced RISC Machine (ARM)
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microprocessor family.
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@section Legal
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This module is written in 2004,2006,2010-2015 by Frank Wille and
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is covered by the vasm copyright without modifications.
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@section Additional options for this module
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This module provides the following additional options:
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@table @option
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@item -a2
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Generate code compatible with ARM V2 architecture.
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@item -a3
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Generate code compatible with ARM V3 architecture.
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@item -a3m
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Generate code compatible with ARM V3m architecture.
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@item -a4
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Generate code compatible with ARM V4 architecture.
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@item -a4t
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Generate code compatible with ARM V4t architecture.
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@item -big
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Output big-endian code and data.
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@item -little
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Output little-endian code and data (default).
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@item -m2
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Generate code for the ARM2 CPU.
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@item -m250
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Generate code for the ARM250 CPU.
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@item -m3
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Generate code for the ARM3 CPU.
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@item -m6
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Generate code for the ARM6 CPU.
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@item -m600
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Generate code for the ARM600 CPU.
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@item -m610
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Generate code for the ARM610 CPU.
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@item -m7
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Generate code for the ARM7 CPU.
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@item -m710
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Generate code for the ARM710 CPU.
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@item -m7500
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Generate code for the ARM7500 CPU.
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@item -m7d
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Generate code for the ARM7d CPU.
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@item -m7di
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Generate code for the ARM7di CPU.
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@item -m7dm
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Generate code for the ARM7dm CPU.
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@item -m7dmi
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Generate code for the ARM7dmi CPU.
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@item -m7tdmi
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Generate code for the ARM7tdmi CPU.
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@item -m8
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Generate code for the ARM8 CPU.
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@item -m810
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Generate code for the ARM810 CPU.
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@item -m9
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Generate code for the ARM9 CPU.
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@item -m9
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Generate code for the ARM9 CPU.
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@item -m920
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Generate code for the ARM920 CPU.
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@item -m920t
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Generate code for the ARM920t CPU.
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@item -m9tdmi
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Generate code for the ARM9tdmi CPU.
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@item -msa1
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Generate code for the SA1 CPU.
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@item -mstrongarm
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Generate code for the STRONGARM CPU.
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@item -mstrongarm110
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Generate code for the STRONGARM110 CPU.
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@item -mstrongarm1100
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Generate code for the STRONGARM1100 CPU.
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@item -opt-adr
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The @code{ADR} directive will be automatically converted into
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@code{ADRL} if required (which inserts an additional
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@code{ADD}/@code{SUB} to calculate an address).
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@item -opt-ldrpc
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The maximum range in which PC-relative symbols can be accessed
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through @code{LDR} and @code{STR} is extended from +/-4KB to +/-1MB
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(or +/-256 Bytes to +/-65536 Bytes when accessing half-words).
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This is done by automatically inserting an additional @code{ADD}
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or @code{SUB} instruction before the @code{LDR}/@code{STR}.
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@item -thumb
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Start assembling in Thumb mode.
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@end table
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@section General
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This backend accepts ARM instructions as described in various ARM CPU
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data sheets. Additionally some architectures support a second, more
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dense, instruction set, called THUMB. There are special directives
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to switch between those two instruction sets.
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The target address type is 32bit.
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Default alignment for instructions is 4 bytes for ARM and 2 bytes for
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THUMB. Sections will be aligned to 4 bytes by default. Data is
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aligned to its natural alignment by default.
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@section Extensions
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This backend extends the selected syntax module by the following
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directives:
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@table @code
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@item .arm
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Generate 32-bit ARM code.
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@item .thumb
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Generate 16-bit THUMB code.
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@end table
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@section Optimizations
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This backend performs the following optimizations and translations for
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the ARM instruction set:
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@itemize @minus
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@item @code{LDR/STR Rd,symbol}, with a distance between symbol and PC larger
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than 4KB, is translated to
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@code{ADD/SUB Rd,PC,#offset&0xff000} +
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@code{LDR/STR Rd,[Rd,#offset&0xfff]}, when allowed by the option
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@code{-opt-ldrpc}.
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@item @code{ADR Rd,symbol} is translated to
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@code{ADD/SUB Rd,PC,#rotated_offset8}.
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@item @code{ADRL Rd,symbol} is translated to
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@code{ADD/SUB Rd,PC,#hi_rotated8} + @code{ADD/SUB Rd,Rd,#lo_rotated8}.
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@code{ADR} will be automatically treated as @code{ADRL} when required
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and when allowed by the option @code{-opt-adr}.
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@item The immediate operand of ALU-instructions will be translated into
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the appropriate 8-bit-rotated value. When rotation alone doesn't
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succeed the backed will try it with inverted and negated values
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(inverting/negating the ALU-instruction too).
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Optionally you may specify the rotate constant yourself, as an
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additional operand.
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@end itemize
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For the THUMB instruction set the following optimizations and translations
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are done:
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@itemize @minus
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@item A conditional branch with a branch-destination being out of range is
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translated into @code{B<!cc> .+4} + @code{B label}.
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@item The @code{BL} instruction is translated into two sub-instructions combining
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the high- and low 22 bit of the branch displacement.
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@end itemize
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@section Known Problems
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Some known problems of this module at the moment:
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@itemize @minus
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@item Only instruction sets up to ARM architecture V4t are supported.
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@end itemize
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@section Error Messages
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This module has the following error messages:
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@itemize @minus
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@item 2001: instruction not supported on selected architecture
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@item 2002: trailing garbage in operand
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@item 2003: label from current section required
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@item 2004: branch offset (%ld) is out of range
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@item 2005: PC-relative load/store (offset %ld) out of range
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@item 2006: cannot make rotated immediate from PC-relative offset (0x%lx)
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@item 2007: constant integer expression required
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@item 2008: constant (0x%lx) not suitable for 8-bit rotated immediate
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@item 2009: branch to an unaligned address (offset %ld)
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@item 2010: not a valid ARM register
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@item 2011: PC (r15) not allowed in this mode
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@item 2012: PC (r15) not allowed for offset register Rm
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@item 2013: PC (r15) not allowed with write-back
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@item 2014: register r%ld was used multiple times
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@item 2015: illegal immediate shift count (%ld)
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@item 2016: not a valid shift register
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@item 2017: 24-bit unsigned immediate expected
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@item 2018: data size %d not supported
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@item 2019: illegal addressing mode: %s
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@item 2020: signed/halfword ldr/str doesn't support shifts
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@item 2021: %d-bit immediate offset out of range (%ld)
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@item 2022: post-indexed addressing mode exptected
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@item 2023: operation not allowed on external symbols
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@item 2024: ldc/stc offset has to be a multiple of 4
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@item 2025: illegal coprocessor operation mode or type: %ld\n
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@item 2026: %d-bit unsigned immediate offset out of range (%ld)
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@item 2027: offset has to be a multiple of %d
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@item 2028: instruction at unaligned address
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@item 2029: TSTP/TEQP/CMNP/CMPP deprecated on 32-bit architectures
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@item 2030: rotate constant must be an even number between 0 and 30: %ld
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@item 2031: %d-bit unsigned constant required: %ld
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@end itemize
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