527 lines
13 KiB
C
527 lines
13 KiB
C
/* cpu.c tr3200 cpu description file */
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/* (c) in 2014 by Luis Panadero Guardeno */
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#include "vasm.h"
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/*#define CPU_DEBUG (1)*/
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#ifdef CPU_DEBUG
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#define OPERAND_DEBUG (1)
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#define INSTR_DEBUG (1)
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#endif
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char *cpu_copyright="vasm TR3200 cpu module v0.1.2 by Luis Panadero Guardeno";
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char *cpuname="tr3200";
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int bitsperbyte=8;
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int bytespertaddr=4;
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mnemonic mnemonics[]={
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#include "opcodes.h"
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};
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int mnemonic_cnt=sizeof(mnemonics)/sizeof(mnemonics[0]);
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static taddr opsize(operand *p, unsigned char num_operands, section *sec, taddr pc);
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/* parse instruction */
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char *parse_instruction(char *s, int *inst_len, char **ext, int *ext_len,
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int *ext_cnt)
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{
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char* inst = s;
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#ifdef CPU_DEBUG
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fprintf(stderr, "parse_inst : \"%.*s\"\n", *inst_len, s);
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#endif
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/*
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while (*s && !isspace((unsigned char)*s))
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s++;
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*inst_len = s - inst; */
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return s;
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}
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/* Sets op if is a valid register */
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static int parse_reg(char **p, int len, operand *op)
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{
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char *rp = skip(*p);
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int reg = -1;
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if (len < 2) {
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return 0;
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}
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if (*rp != '%') {
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return 0;
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}
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rp++;
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if (tolower((unsigned char)rp[0]) != 'r') {
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/* Could be y, bp, sp, ia or flags */
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if (len == 2 && tolower((unsigned char)rp[0]) == 'y') {
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rp++;
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*p = skip(rp);
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op->type = OP_GPR;
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op->reg = 11;
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return 1;
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} else if ( len == 3 && (tolower((unsigned char)rp[0]) == 'b')
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&& (tolower((unsigned char)rp[1]) == 'p') ) {
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rp++; rp++;
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*p = skip(rp);
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op->type = OP_GPR;
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op->reg = 12;
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return 1;
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} else if ( len == 3 && (tolower((unsigned char)rp[0]) == 's')
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&& (tolower((unsigned char)rp[1]) == 'p') ) {
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rp++; rp++;
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*p = skip(rp);
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op->type = OP_GPR;
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op->reg = 13;
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return 1;
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} else if ( len == 3 && (tolower((unsigned char)rp[0]) == 'i')
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&& (tolower((unsigned char)rp[1]) == 'a') ) {
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rp++; rp++;
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*p = skip(rp);
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op->type = OP_GPR;
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op->reg = 14;
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return 1;
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} else if ( len == 6
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&& (tolower((unsigned char)rp[0]) == 'f')
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&& (tolower((unsigned char)rp[1]) == 'l')
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&& (tolower((unsigned char)rp[2]) == 'a')
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&& (tolower((unsigned char)rp[3]) == 'g')
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&& (tolower((unsigned char)rp[4]) == 's')
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) {
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rp += 5;
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*p = skip(rp);
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op->type = OP_GPR;
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op->reg = 14;
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return 1;
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}
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/* It's not a register */
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return 0;
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}
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rp++;
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/* Get number */
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if (len < 2 || sscanf(rp, "%u", ®) != 1) {
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return 0;
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}
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/* "%r0 .. %r15" are valid */
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if (reg < 0 || reg > 15) {
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return 0;
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}
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/* skip digits and return new pointer together with register number */
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while ( isdigit((unsigned char)*rp) ) {
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rp++;
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}
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*p = skip(rp);
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op->type = OP_GPR;
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op->reg = reg;
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return 1;
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}
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/* Parses operands and reads expressions
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* *p string
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* len string length
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* *op operand
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* requires Type of operand expected
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*/
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int parse_operand(char *p, int len, operand *op, int requires)
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{
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op->type = NO_OP;
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#ifdef OPERAND_DEBUG
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fprintf(stderr, "parse_operand (reqs=%02x): \"%.*s\"\t",
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(unsigned)requires, len, p);
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#endif
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/* Try to grab the register */
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if (1 != parse_reg(&p, len, op) ) {
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#ifdef OPERAND_DEBUG
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fprintf(stderr, "imm\t");
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#endif
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/* Its not a register, should be a immediate value or a expression */
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if(p[0]=='#') { /* Immediate value */
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expr *tree;
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#ifdef OPERAND_DEBUG
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fprintf(stderr, "# ");
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#endif
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op->type = OP_IMM;
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p=skip(p+1);
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tree = parse_expr(&p);
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if (!tree) { /* It's not a valid expresion */
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return PO_NOMATCH;
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}
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op->value = tree;
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} else { /* expresion that would be a immediate value */
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#ifdef OPERAND_DEBUG
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fprintf(stderr, "expr\t");
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#endif
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op->type = OP_IMM;
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int parent=0;
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expr *tree;
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/*
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if (*p=='(') {
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parent=1;
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p=skip(p+1);
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}
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*/
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tree = parse_expr(&p);
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if (!tree) { /* It's not a valid expresion */
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return PO_NOMATCH ;
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}
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/* Inside of a ( ) */
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/*
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p=skip(p);
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if(parent) {
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if(*p!=')'){
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cpu_error(0);
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return 0;
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} else
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p=skip(p+1);
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}
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*/
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op->value=tree;
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}
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}
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#ifdef OPERAND_DEBUG
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fprintf(stderr, "(type=%02x)\n", (unsigned) op->type);
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#endif
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if(requires == op->type) { /* Matched type */
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return PO_MATCH;
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}
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return PO_NOMATCH; /* Ops! Not match */
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}
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/* Convert an instruction into a DATA atom including relocations,
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if necessary. */
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dblock *eval_instruction (instruction *p, section *sec, taddr pc)
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{
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/* Calc instruction size */
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size_t size = instruction_size(p, sec, pc);
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dblock *db = new_dblock();
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mnemonic m = mnemonics[p->code];
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unsigned char *opcode, *d; /* Data */
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taddr val;
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unsigned char ml_bits = 0;
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unsigned char num_operands = 0;
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unsigned char srn = 0; /* Size of Rn */
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operand* rn = NULL;
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symbol *base = NULL;
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int btype;
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#ifdef INSTR_DEBUG
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fprintf(stderr, "eval_instruction code \"%s\" ", m.name);
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#endif
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num_operands += (m.operand_type[0] != NO_OP)? 1 : 0;
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num_operands += (m.operand_type[1] != NO_OP)? 1 : 0;
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num_operands += (m.operand_type[2] != NO_OP)? 1 : 0;
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if (num_operands > 0) {
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rn = p->op[m.ext.rn_pos];
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}
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#ifdef INSTR_DEBUG
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fprintf(stderr, "P%d ", num_operands);
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if (num_operands > 0)
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fprintf(stderr, "rn type=%02x ", (unsigned) rn->type);
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#endif
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/* See if Rn is an immediate to set ML bits*/
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if (rn != NULL && rn->type == OP_IMM) {
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srn = opsize(rn, num_operands, sec, pc);
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ml_bits = 2 | (srn == 4);
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}
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ml_bits = ml_bits << 6; /* Emplace ML bits */
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#ifdef INSTR_DEBUG
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fprintf(stderr, "IMM=%d ", srn);
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fprintf(stderr, "ml %02x ", ml_bits);
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#endif
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db->size=size;
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db->data = mymalloc(size); /* allocate for the data block */
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memset(db->data, 0, db->size);
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/* Here to write data ! */
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d = db->data;
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d[3] = m.ext.opcode; /* Common part */
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d[2] = ml_bits;
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switch (num_operands) {
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case 3: /* format P3 */
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/* Rn is always at the LSBytes side */
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if( rn->type == OP_GPR) { /* Is a register */
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d[0] = (rn->reg) & 0xF;
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} else if (ml_bits == 0x80 ) { /* ML are 10 -> immediate */
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eval_expr(rn->value, &val, sec, pc);
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#ifdef INSTR_DEBUG
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fprintf(stderr, "val %04x ", val);
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#endif
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d[1] = (val >>8) & 0x3F;
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d[0] = (val ) & 0xFF;
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} else { /* 32 bit immediate */
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eval_expr(rn->value, &val, sec, pc);
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#ifdef INSTR_DEBUG
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fprintf(stderr, "val %08x ", val);
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#endif
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d[7] = (val >>24) & 0xFF;
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d[6] = (val >>16) & 0xFF;
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d[5] = (val >>8 ) & 0xFF;
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d[4] = (val ) & 0xFF;
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}
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if (m.ext.rn_pos == 1) { /* Special case of STORE */
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d[1] |= (p->op[0]->reg & 0xF) << 6;
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d[2] |= (p->op[0]->reg & 0xF) >> 2;
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d[2] |= (p->op[2]->reg) << 2; /* rd */
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} else {
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d[1] |= (p->op[1]->reg & 0xF) << 6;
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d[2] |= (p->op[1]->reg & 0xF) >> 2;
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d[2] |= (p->op[0]->reg) << 2; /* rd */
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}
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break;
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case 2: /* format P2 */
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if( rn->type == OP_GPR) { /* Is a register */
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d[0] = (rn->reg) & 0xF;
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} else if (ml_bits == 0x80 ) { /* ML are 10 -> immediate */
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eval_expr(rn->value, &val, sec, pc);
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/* CALL/JUMP stuff */
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if (m.ext.opcode == 0x4B || m.ext.opcode == 0x4C ) {
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val = val >> 2; /* CALL/JMP does a left shift of two bits */
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}
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#ifdef INSTR_DEBUG
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fprintf(stderr, "val %06x ", val);
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#endif
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d[2] |= (val >>16) & 0x03;
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d[1] = (val >>8) & 0xFF;
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d[0] = (val ) & 0xFF;
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} else { /* 32 bit immediate */
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eval_expr(rn->value, &val, sec, pc);
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#ifdef INSTR_DEBUG
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fprintf(stderr, "val %08x ", val);
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#endif
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d[7] = (val >>24) & 0xFF;
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d[6] = (val >>16) & 0xFF;
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d[5] = (val >>8 ) & 0xFF;
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d[4] = (val ) & 0xFF;
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}
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if (m.ext.rn_pos == 0) { /* Special case of STORE */
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d[2] |= (p->op[1]->reg) << 2;
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} else {
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d[2] |= (p->op[0]->reg) << 2;
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}
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break;
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case 1: /* format P1 */
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if( rn->type == OP_GPR) { /* Is a register */
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d[0] = (rn->reg) & 0xF;
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} else if (ml_bits == 0x80 ) { /* ML are 10 -> immediate */
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if (!eval_expr(rn->value, &val, sec, pc))
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btype = find_base(rn->value, &base, sec, pc);
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/* CALL/JUMP stuff */
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if (m.ext.opcode >= 0x27 && m.ext.opcode <= 0x28 ) {
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if (base != NULL && btype == BASE_OK) {
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if (is_pc_reloc(base, sec))
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add_extnreloc_masked(&db->relocs, base, val-4, REL_PC,
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0, 22, 0, 0xfffffc);
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else if (LOCREF(base))
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val = val - pc - 4; /* Relative jump/call (%pc has been increased) */
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base = NULL;
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}
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else
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val = val - pc - 4; /* Relative jump/call (%pc has been increased) */
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val = val >> 2; /* CALL/JMP does a left shift of two bits */
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} else if (m.ext.opcode >= 0x25 && m.ext.opcode <= 0x26 ) {
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if (base != NULL && btype != BASE_ILLEGAL) {
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add_extnreloc_masked(&db->relocs, base, val,
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btype == BASE_PCREL ? REL_PC : REL_ABS,
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0, 22, 0, 0xfffffc);
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base = NULL;
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}
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val = val >> 2; /* CALL/JMP does a left shift of two bits */
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}
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#ifdef INSTR_DEBUG
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fprintf(stderr, "val %06x ", val);
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#endif
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d[2] |= (val >>16) & 0x3F;
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d[1] = (val >>8) & 0xFF;
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d[0] = (val ) & 0xFF;
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} else { /* 32 bit immediate */
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eval_expr(rn->value, &val, sec, pc);
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/* CALL/JUMP stuff */
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if (m.ext.opcode >= 0x27 && m.ext.opcode <= 0x28 ) {
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val = val - pc - 4; /* Relative jump/call */
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}
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#ifdef INSTR_DEBUG
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fprintf(stderr, "val %08x ", val);
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#endif
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d[7] = (val >>24) & 0xFF;
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d[6] = (val >>16) & 0xFF;
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d[5] = (val >>8 ) & 0xFF;
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d[4] = (val ) & 0xFF;
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}
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break;
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case 0: /* format NP */
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#ifdef INSTR_DEBUG
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fprintf(stderr, "NP ");
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#endif
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default:
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;
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}
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#ifdef INSTR_DEBUG
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{
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int i;
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for(i= db->size -1; i >= 0; i-- ) {
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fprintf(stderr, "%02X ", d[i]);
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}
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}
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fprintf(stderr, "\n");
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#endif
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return db;
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}
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/* Create a dblock (with relocs, if necessary) for size bits of data. */
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dblock *eval_data(operand *op, size_t bitsize, section *sec, taddr pc)
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{
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dblock *new=new_dblock();
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taddr val;
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new->size = bitsize >> 3;
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new->data = mymalloc(new->size);
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#ifdef CPU_DEBUG
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fprintf(stderr, "eval_data ");
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#endif
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if(op->type != OP_IMM) { /* ??? */
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#ifdef CPU_DEBUG
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fprintf(stderr, "!= OP_IMM\n");
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#endif
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ierror(0);
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}
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if(bitsize!=8 && bitsize!=16 && bitsize!=32) {
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#ifdef CPU_DEBUG
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fprintf(stderr, "bad data size\n");
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#endif
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cpu_error(2); /* Invalid data size */
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}
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if(!eval_expr(op->value, &val, sec, pc) ) {
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symbol *base;
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int btype;
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btype = find_base(op->value, &base, sec, pc);
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if (base)
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add_extnreloc(&new->relocs, base, val,
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btype==BASE_PCREL ? REL_PC : REL_ABS, 0, bitsize, 0);
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else if (btype != BASE_NONE)
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general_error(38); /* illegal relocation */
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}
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if(bitsize == 8){
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new->data[0] = val & 0xFF;
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} else if (bitsize == 16){
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new->data[1] = (val>>8) & 0xFF;
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new->data[0] = val & 0xFF;
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} else if (bitsize == 32){
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new->data[3] = (val>>24) & 0xFF;
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new->data[2] = (val>>16) & 0xFF;
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new->data[1] = (val>>8) & 0xFF;
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new->data[0] = val & 0xFF;
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}
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return new;
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}
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/* Size of a operand
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* *p operand
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* num_operand Total number of operands
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* */
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static taddr opsize(operand *p, unsigned char num_operands, section *sec, taddr pc)
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{
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taddr val = 0;
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if(!p) {
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return 0;
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} else if (p->type == OP_IMM ) {
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eval_expr(p->value, &val, sec, pc);
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if (num_operands == 3
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&& (val < -8192 || val > 8191) ) { /* 14 bits */
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return 4; /* 32 bit immediate */
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} else if (num_operands == 2
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&& (val < -131072 || val > 131071) ) { /* 18 bits */
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return 4; /* 32 bit immediate */
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} else if (num_operands == 1
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&& (val < -2097152 || val > 2097151) ) { /* 22 bits */
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return 4; /* 32 bit immediate */
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}
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}
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return 0;
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}
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/* Calculate the size of the current instruction; must be identical
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to the data created by eval_instruction. */
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size_t instruction_size (instruction *p, section *sec, taddr pc)
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{
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size_t size = 4; /* four bytes */
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unsigned char num_operands = 0;
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num_operands += (p->op[0] != 0)? 1 : 0;
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num_operands += (p->op[1] != 0)? 1 : 0;
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num_operands += (p->op[2] != 0)? 1 : 0;
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size += opsize(p->op[0], num_operands, sec, pc);
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size += opsize(p->op[1], num_operands, sec, pc);
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size += opsize(p->op[2], num_operands, sec, pc);
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return size;
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}
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operand *new_operand()
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{
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operand *new = mymalloc(sizeof(*new));
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new->type=-1;
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return new;
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}
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/* return true, if initialization was successfull */
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int init_cpu()
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{
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return 1;
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}
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/* return true, if the passed argument is understood */
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int cpu_args(char *p)
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{
|
|
/* no args */
|
|
return 0;
|
|
}
|
|
|
|
/* parse cpu-specific directives; return pointer to end of
|
|
cpu-specific text */
|
|
char *parse_cpu_special(char *s)
|
|
{
|
|
/* no specials */
|
|
return s;
|
|
}
|