This chapter documents the backend for the MOS/Rockwell 6502
microprocessor family. It also supports the Rockwell/WDC 65C02 and the
Hudson Soft HuC6280 instruction sets.

@section Legal

    This module is written in 2002,2006,2008-2012,2014-2018 by Frank Wille
    and is covered by the vasm copyright without modifications.


@section Additional options for this module

This module provides the following additional options:

@table @option
    @item -6280
        Recognize all HuC6280 instructions.
    @item -c02
        Recognize all 65C02 instructions. This excludes DTV (@option{-dtv})
        and illegal (@option{-illegal}) instructions.
    @item -dtv
        Recognize the three additional C64-DTV instructions.
    @item -illegal
        Allow 'illegal' 6502 instructions to be recognized.
    @item -opt-branch
        Enables 'optimization' of B<cc> branches into
        "B<!cc> *+3 ; JMP label" sequences when necessary.
    @item -wdc02
        Recognize all 65C02 instructions and the WDC65C02 extensions
        (RMB,SMB,BBR,BBS,STP,WAI).
@end table

@section General

This backend accepts 6502 family instructions as described in
the instruction set reference manuals from MOS and Rockwell, which are valid
for the following CPUs: 6502 - 6518, 6570, 6571, 6702, 7501, 8500, 8502.

Optionally accepts 65C02 family instructions as decribed in the
instruction set reference manuals from Rockwell and WDC. Also supports
the WDC extensions in the W65C02 and W65C134.

Optionally accepts 65CE02 family instructions as decribed in the
instruction set reference manuals from Commodore Semiconductor Group.

Optionally accepts HuC6280 instructions as described in the instruction
set reference manuals from Hudson Soft.

The target address type is 16 bit.

Instructions consist of one up to three bytes for the standard 6502 family
(up to 7 bytes for the 6280) and require no alignment.
There is also no alignment requirement for sections and data.

All known mnemonics for illegal instructions are optionally recognized (e.g.
@code{dcm} and @code{dcp} refer to the same instruction). Some illegal
insructions (e.g. @code{$ab}) are known to show unpredictable behaviour,
or do not always work the same on different CPUs.

@section Extensions

This backend provides the following specific extensions:

@itemize @minus

@item The parser understands a lo/hi-modifier to select low- or high-byte
 of a 16-bit word. The character @code{<} is used to select the low-byte
 and @code{>} for the high-byte. It has to be the first character before
 an expression.

@item When applying the operation @code{/256}, @code{%256} or @code{&256}
 on a label, an appropriate lo/hi-byte relocation will automatically be
 generated.

@end itemize

This backend extends the selected syntax module by the following
directives:

@table @code
@item setdp <expr>
      Set the current base address of the zero/direct page for
      optimizations from absolute to zero-page addressing modes.
      Example: set it to @code{$2000} for the HuC6280/PC-Engine.
@end table

@section Optimizations

This backend performs the following operand optimizations:

@itemize @minus

@item Branches, where the destination is out of range, are translated
 into @code{B<!cc> *+3} and an absolute @code{JMP} instruction.

@end itemize

@section Known Problems

    Some known problems of this module at the moment:

@itemize @minus

@item None.

@end itemize

@section Error Messages

This module has the following error messages:

@itemize @minus

@item 2001: instruction not supported on selected architecture
@item 2002: trailing garbage in operand
@item 2003: missing closing parenthesis in addressing mode
@item 2004: data size %d not supported
@item 2005: relocation does not allow hi/lo modifier
@item 2006: operand doesn't fit into 8-bits
@item 2007: branch destination out of range
@item 2008: illegal bit number

@end itemize